Digital Electronics | A.P.Godse,Dr.D.A.Godse
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Digital Electronics

Index

Minimization Techniques and Logic Gates Minimization Techniques : Boolean postulates and laws - De-Morgan's theorem - Principle of duality - Boolean expression - Minimization of Boolean expressions - Minterm - Maxterm - Sum of Products (SOP) - Product of Sums (POS) - Karnaugh map minimization - Don't care conditions - Quine-McCluskey method of minimization. Logic Gates : AND, OR, NOT, NAND, NOR, Exclusive-OR and Exclusive-NOR- Implementations of logic functions using gates, NAND-NOR implementations - Multilevel gate implementations - Multioutput gate implementations. TTL and CMOS logic and their characteristics - Tristate gates. Combinational Circuits Design procedure - Half adder - Full adder - Half subtractor - Full subtractor - Parallel binary adder, Parallel binary subtractor - Fast adder - Carry look ahead adder - Serial adder/subtractor - BCD adder - Binary multiplier - Binary divider - Multiplexer/demultiplexer - Decoder - Encoder - Parity checker - Parity generators - Code converters - Magnitude comparator. Sequential Circuits Latches, Flip-flops - SR, JK, D, T and Master-Slave - Characteristic table and equation - Application table - Edge triggering - Level triggering - Realization of one flip-flop using other flip-flops - Serial adder/subtractor - Asynchronous ripple or serial counter - Asynchronous up/down counter - Synchronous counters - Synchronous up/down counters - Programmable counters - Design of synchronous counters : State diagram - State table - State minimization - State assignment - Excitation table and maps - Circuit implementation - Modulo-n counter, Registers - Shift registers - Universal shift registers - Shift register counters - Ring counter - Shift counters - Sequence generators. Memory Devices Classification of memories - ROM - ROM organization - PROM - EPROM - EEPROM - EAPROM, RAM - RAM organization - Write operation - Read operation-Memory cycle - Timing waveforms - Memory decoding - Memory expansion - Static RAM cell - Bipolar RAM cell - MOSFET RAM cell - Dynamic RAM cell - Programmable Logic Devices - Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA, PAL. Synchronous and Asynchronous Sequential CircuitsSynchronous Sequential Circuits : General model - Classification - Design - Use of algorithmic state machine - Analysis of synchronous sequential circuits. Asynchronous Sequential Circuits : Design of fundamental mode and pulse mode circuits - Incompletely specified state machines - Problems in asynchronous circuits - Design of hazard free switching circuits. Design of combinational and sequential circuits using VERILOG.

2013 Regulation

Author : A.P.Godse,Dr.D.A.Godse

Language : English

Publisher : TechnicalPublications

ISBN : 9789350997017

Details
Publication Technical Publications
Writer A.P.Godse,Dr.D.A.Godse
ISBN-10 9350997010
ISBN-13 9789350997017

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